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| 100 MHz to 6 GHz TruPwrTM Detector ADL5500 FEATURES True rms response Excellent temperature stability 0.1 dB accuracy vs. temperature over top 8 dB of input range Up to 30 dB input dynamic range at 3.9 GHz 50 input impedance 1250 mV rms, +15 dBm, maximum input Single-supply operation: 2.7 V to 5.5 V Low power: 3 mW at 3 V supply RoHS compliant 5 1 OUTPUT (V) 0.1 05546-001 APPLICATIONS Measurement of CDMA2000, W-CDMA, and QPSK-/QAMbased OFDM, and other complex modulation waveforms RF transmitter or receiver power measurement 0.03 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 1. Output vs. Input Level, Supply 3 V, Frequency 1.9 GHz GENERAL DESCRIPTION The ADL5500 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains from 100 MHz to 6 GHz. It is easy to apply, requiring only a single supply between 2.7 V and 5.5 V and a power supply decoupling capacitor. The input is internally ac-coupled and has a nominal input impedance of 50 . The output is a linear-responding dc voltage with a conversion gain of 6.4 V/V rms at 900 MHz. The on-chip, 1 k series resistance at the output combined with an external shunt capacitor creates a low-pass filter response that reduces the residual ripple in the dc output voltage. The ADL5500 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as CDMA2000, W-CDMA, and QPSK/QAMbased OFDM waveforms. The ADL5500 offers excellent temperature stability with near 0 dB measurement error across temperature. The high accuracy range, centered around +3 dBm at 900 MHz, offers 0.1 dB error from -40C to +85C over an 8.5 dB range. The ADL5500 reduces calibration requirements with low drift across a 30 dB range over temperature and process variations. The ADL5500 operates from -40C to +85C and is available in a 4-ball, 1.0 mm x 1.0 mm wafer-level chip scale package. It is fabricated on a proprietary high fT silicon bipolar process. FUNCTIONAL BLOCK DIAGRAM ADL5500 RFIN x2 i INTERNAL FILTER CAPACITOR VPOS TRANSCONDUCTANCE CELLS x2 i ERROR AMP BUFFER 1k 05546-002 VRMS COMM Figure 2. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADL5500 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Circuit Description......................................................................... 14 Filtering........................................................................................ 14 Applications..................................................................................... 15 Basic Connections ...................................................................... 15 Output Swing .............................................................................. 15 Linearity....................................................................................... 15 Input Coupling Using a Series Resistor................................... 16 Multiple RF Inputs ..................................................................... 16 Selecting the Output Low-Pass Filter Network ...................... 16 Power Consumption and Power-On/-Off Response............. 16 Output Drive Capability and Buffering................................... 17 VRMS Output Offset ................................................................. 17 Device Calibration and Error Calculation.............................. 18 Calibration for Improved Accuracy......................................... 18 Drift over a Reduced Temperature Range .............................. 19 Operation Above 4.0 GHz......................................................... 19 Device Handling......................................................................... 19 Evaluation Board ........................................................................ 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 2/06--Rev 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 2............................................................................ 7 Changes to Figure 5.......................................................................... 9 Changes to Figure 28 and Figure 31............................................. 13 Changes to Figure 35 Caption....................................................... 15 Changes to Power Consumption and Power-On/-Off Response Section ............................................................................ 16 Changes to Figure 48...................................................................... 20 Changes to Ordering Guide .......................................................... 22 7/05--Revision 0: Initial Version Rev. A | Page 2 of 24 ADL5500 SPECIFICATIONS TA = 25C, VS = 3.0 V, CFLT = 10 nF, light condition 600 LUX, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE RMS CONVERSION (f = 100 MHz) Input Impedance Input Return Loss Dynamic Range 1 0.1 dB Error 2 0.25 dB Error 3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept 4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity VS = 5 V PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to output VRMS -20 2.43 0.14 0.0032 -0.0042 75||1.4 12.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C 8 19 24 24.5 29 27.5 33 5 -19.5 6.9 0.03 2.8 0.16 0.0020 -0.0023 Condition Input RFIN Input RFIN to output VRMS Min 100 Typ Max 6000 Unit MHz ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V/V rms V mV V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C 94||3 10 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept VS = 5 V 5 17.5 20 25 29 28.5 33 6 -18.5 6.1 4.6 0.03 +100 7.2 RMS CONVERSION (f = 450 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. A | Page 3 of 24 ADL5500 Parameter RMS CONVERSION (f = 900 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to output VRMS Min Typ 62||1.1 13 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA +85C -40C TA +25C Input RFIN to output VRMS 8.5 19.5 23 24.5 29 28 32 6 -19 6.4 0.04 2.61 0.15 0.0018 -0.0023 43||0.9 11.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C 7 20 23 26 30 31.5 33 8 -19.5 5.0 0.02 2.02 0.11 0.0017 -0.0031 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C RMS CONVERSION (f = 1900 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. A | Page 4 of 24 ADL5500 Parameter RMS CONVERSION (f = 2350 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to output VRMS Min Typ 37||0.9 9 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to output VRMS 5 5 10 28.5 32 32 36 8 -19.5 4.5 0.02 1.82 0.11 0.0027 -0.0046 34||0.8 8.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN =+5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C 5 5 8.5 28.5 32 33 36 9 -19.5 4.2 0.02 1.67 0.1 0.0030 -0.0049 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C RMS CONVERSION (f = 2700 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. A | Page 5 of 24 ADL5500 Parameter RMS CONVERSION (f = 3900 MHz) Input Impedance Input Return Loss Dynamic Range1 0.1 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to output VRMS Min Typ 30||0.6 9 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 0.25 dB error3 1 dB error3 VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C No signal at RFIN -40C < TA < +85C No signal at RFIN 5 2.7 1.0 2 5.5 8 28.5 32 34 36.5 12 -17 3.2 0.02 1.28 0.08 0.0035 -0.0066 40 150 5.5 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C mV V mA OUTPUT OFFSET POWER SUPPLIES Operating Range Quiescent Current 1 2 The available output swing, and hence the dynamic range, is altered by the supply voltage; see Figure 8. Error referred to delta from 25C response; see Figure 16 through Figure 21. 3 Error referred to best-fit line at 25C 4 Calculated using linear regression. 5 Supply current is input level dependant; see Figure 6. Rev. A | Page 6 of 24 ADL5500 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VS VRMS RFIN Equivalent Power, re 50 Internal Power Dissipation JA (WLCSP) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V, VS 1.25 V rms 15 dBm 150 mW 260C/W 125C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 24 ADL5500 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BUMP 1 INDICATOR VRMS VPOS 1 4 05546-003 COMM RFIN 2 3 TOP VIEW (BUMP SIDE DOWN) Not to Scale Figure 3. 4-Ball WLCSP Pin Configuration Table 3. Pin Function Descriptions Ball No. 1 2 3 4 Mnemonic Description VRMS Output Pin. Rail-to-rail voltage output with limited current drive capability. The output has an internal 1 k series resistance. High resistive loads are recommended to preserve output swing. COMM Device Ground Pin. RFIN Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 50 input impedance. VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V. Rev. A | Page 8 of 24 ADL5500 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VS = 5.0 V, CFLT = 10 nF, light condition 600 LUX, Colors: black = +25C, blue = -40C, red = +85C, unless otherwise noted. 10 3 2 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 3900MHz 1 1 OUTPUT (V) ERROR (dB) 0.1 05546-004 0 0.03 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 4. Output vs. Input Level, Frequencies 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 3900 MHz, Supply 5.0 V 5.0 4.5 4.0 Figure 7. Linearity Error vs. Input Level, Frequencies 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 3900 MHz, Supply 5.0 V 10 5.5V 5.0V 2.7V 3.5 3.0V OUTPUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 INPUT (V rms) 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 3900MHz 1.2 1.4 05546-005 OUTPUT (V) 1 0.1 05546-008 0.03 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 5. Output vs. Input Level (Linear Scale), Frequencies 100 MHz, 450 MHz, 900 MHz,1900 MHz, 2350 MHz, 2700 MHz, and 3900 MHz, Supply 5.0 V 11 10 9 Figure 8. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz 25 SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 3.0V 20 RETURN LOSS (dB) 5.0V 15 10 05546-006 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 INPUT (V rms) 5 0 1 2 3 FREQUENCY (GHz) 4 5 6 Figure 6. Supply Current vs. Input Level, Supplies 3.0 V and 5.0 V, Temperatures -40C, +25C, and +85C Figure 9. Return Loss vs. Frequency Rev. A | Page 9 of 24 05546-009 05546-007 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 3900MHz -1 -2 ADL5500 3 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 05546-010 -2 05546-013 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 10. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 450 MHz, Supply 5.0 V 3 Figure 13. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 2350 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 05546-011 -2 05546-014 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 11. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 900 MHz, Supply 5.0 V 3 Figure 14. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 2700 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 05546-012 -2 05546-015 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 12. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 1900 MHz, Supply 5.0 V Figure 15. Temperature Drift Distributions for 55 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 3900 MHz, Supply 5.0 V Rev. A | Page 10 of 24 ADL5500 3 3 2 2 1 ERROR (dB) ERROR (dB) 05546-016 1 0 0 -1 -1 -2 -2 05546-019 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 16. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 450 MHz, Supply 5.0 V 3 Figure 19. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 2350 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 05546-017 1 0 0 -1 -1 -2 -2 05546-020 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 17. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 900 MHz, Supply 5.0 V 3 Figure 20. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 2700 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 05546-018 -2 05546-021 -3 -25 -20 -15 -10 -5 0 5 10 15 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 18. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 1900 MHz, Supply 5.0 V Figure 21. Output Delta from +25C Output Voltage for 55 Devices at -40C and +85C, Frequency 3900 MHz, Supply 5.0 V Rev. A | Page 11 of 24 ADL5500 10 CW QPSK, 4.8dB CF 8PSK, 4.8dB CF 16QAM, 6.3dB CF 64QAM, 7.4dB CF 3.0 2.5 2.0 1.5 1.0 CW QPSK, 4.8dB CF 8PSK, 4.8dB CF 16QAM, 6.3dB CF 64QAM, 7.4dB CF 1 ERROR (dB) 0.1 05546-022 OUTPUT (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -25 -20 -15 -10 -5 0 5 10 05546-025 0.03 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 22. Output vs. Input Level with Different Waveforms, 10 MHz Signal BW for All Modulated Signals, Supply 5.0 V, Frequency 1900 MHz 3.0 2.5 2.0 1.5 1.0 CW BPSK, 11dB CF QPSK, 11dB CF 16QAM, 12dB CF 64QAM, 11dB CF Figure 25. Error from CW Linear Reference vs. Input with Different Waveforms, 10 MHz Signal BW for All Modulated Signals, Supply 5.0 V, Frequency 1900 MHz 3.0 2.5 2.0 1.5 1.0 CW BPSK, 11dB CF QPSK, 11dB CF 16QAM, 12dB CF 64QAM, 11dB CF ERROR (dB) ERROR (dB) 0.5 0 -0.5 -1.0 -1.5 -2.0 05546-023 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -25 -20 -15 -10 -5 0 5 10 05546-026 -2.5 -3.0 -25 -20 -15 -10 -5 0 5 10 INPUT (dBm) INPUT (dBm) Figure 23. Error from CW Linear Reference vs. Input Level for Various 802.16 OFDM Waveforms at 2.35 GHz, 10 MHz Signal BW and 256 Subcarriers for All Modulated Signals, Supply 5.0 V 3.0 CW 12.2kbps, DPCCH (-5.46dB, 15ksps) + DPDCH (0dB, 60ksps), 3.4dB CF 64kbps, DPCCH (-9.54dB, 15ksps) + DPDCH (0dB, 240ksps), 3.4dB CF 144kbps, DPCCH (-11.48dB, 15ksps) + DPDCH (0dB, 480ksps), 3.3dB CF 384kbps, DPCCH (-11.48dB, 15ksps) + DPDCH (0dB, 960ksps), 3.3dB CF 768kbps, DPCCH (-11.48dB, 15ksps) + DPDCH1 + 2 (0dB, 960ksps), 5.8dB CF Figure 26. Error from CW Linear Reference vs. Input Level for Various 802.16 OFDM Waveforms at 3.5 GHz, 10 MHz Signal BW and 256 Subcarriers for All Modulated Signals, Supply 5.0 V 3.0 2.0 2.0 1.0 1.0 ERROR (dB) ERROR (dB) 0 0 CW PICH, 4.7dB CF PICH + FCH (9.6kbps), 4.8dB CF PICH + FCH (9.6kbps) + DCCH, 6.3dB CF PICH + FCH (9.6kbps) + SCH (153.6kbps), 6.7dB CF PICH + FCH (9.6kbps) + DCCH + SCH (153.6kbps), 7.6dB CF -20 -15 -10 -5 0 5 10 -1.0 -1.0 -2.0 05546-024 -2.0 -3.0 -25 -20 -15 -10 -5 0 5 10 -3.0 -25 INPUT (dBm) INPUT (dBm) Figure 24. Error from CW Linear Reference vs. Input with Various WCDMA Up Link Waveforms at 1900 MHz Rev. A | Page 12 of 24 Figure 27. Error from CW Linear Reference vs. Input with Various CDMA2000 Reverse Link Waveforms at 900 MHz 05546-027 ADL5500 HPE3631A POWER SUPPLY HP8110A PULSE GENERATOR 50 AD811 732 ADL5500 TEK P6204 FET PROBE 1 C4 2 COMM RFIN 3 VRMS VPOS 4 C2 100pF C1 0.1F ADL5500 TEK P6204 FET PROBE 1 C4 2 COMM RFIN 3 VRMS VPOS 4 C2 100pF C1 0.1F TEK TDS784C SCOPE Figure 28. Hardware Configuration for Output Response to Modulated Pulse Input 900MHz PULSED RFIN Figure 31. Hardware Configuration for Output Response to Power Supply Gating Measurements VPOS 400mV rms RF INPUT 250mV rms 160mV rms VRMS 500mV PER VERTICAL DIVISION 05546-029 400mV rms RF INPUT 250mV rms 160mV rms VRMS 500mV PER VERTICAL DIVISION 70mV rms 70mV rms Figure 29. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor 900MHz PULSED RFIN Figure 32. Output Response to Gating on Power Supply for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 F Filter Capacitor 400mV rms RF INPUT 250mV rms 160mV rms VRMS 500mV PER VERTICAL DIVISION 70mV rms Figure 30. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 F Filter Capacitor 05546-030 400s PER HORIZONTAL DIVISION Rev. A | Page 13 of 24 05546-032 400s PER HORIZONTAL DIVISION 200s PER HORIZONTAL DIVISION 05546-031 TEK TDS784C SCOPE 05546-028 HP8648B SIGNAL GENERATOR HP8648B SIGNAL GENERATOR ADL5500 CIRCUIT DESCRIPTION The ADL5500 is an rms-responding (mean power) detector that provides an approach to the exact measurement of RF power that is independent of waveform. It achieves this function by using a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high-gain error amplifier. The signal to be measured is applied to the input of the first squaring cell through the input matching network. The input is matched to offer a broadband 50 input impedance from 100 MHz to 6 GHz. The input matching network has a high-pass corner frequency of approximately 90 MHz. The ADL5500 responds to the voltage, VIN, at its input by squaring this voltage to generate a current proportional to VIN2. This current is applied to an internal load resistor in parallel with a capacitor, followed by a low-pass filter, which extracts the mean of VIN2. Although essentially voltage responding, the associated input impedance calibrates this port in terms of equivalent power. Therefore, 1 mW corresponds to a voltage input of 224 mV rms referenced to 50 . Because both the squaring cell input impedance and the input matching network are frequency dependent, the conversion gain is a function of signal frequency. The voltage across the low-pass filter, whose frequency can be arbitrarily low, is applied to one input of an error-sensing amplifier. A second identical voltage-squaring cell is used to close a negative feedback loop around this error amplifier. This second cell is driven by a fraction of the quasi-dc output voltage of the ADL5500. When the voltage at the input of the second squaring cell is equal to the rms value of VIN, the loop is in a stable state, and the output then represents the rms value of the input. By completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several benefits arise. First, scaling effects in these cells cancel; therefore, the overall calibration can be accurate, even though the open-loop response of the squaring cells taken separately need not be. Note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scaling. Second, the tracking in the responses of the dual cells remains very close over temperature, leading to excellent stability of calibration. The squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. However, the dynamic range of such a system is small due in part to the much larger dynamic range at the output of the squaring cells. There are practical limitations to the accuracy of sensing very small error signals at the bottom end of the dynamic range, arising from small random offsets that limit the attainable accuracy at small inputs. On the other hand, the squaring cells in the ADL5500 have a Class-AB aspect; the peak input is not limited by its quiescent bias condition but is determined mainly by the eventual loss of square-law conformance. Consequently, the top end of their response range occurs at a large input level (approximately 700 mV rms) while preserving a reasonably accurate square-law response. The maximum usable range is, in practice, limited by the output swing. The rail-to-rail output stage can swing from a few millivolts above ground to within 100 mV below the supply. An example of the output induced limit, given a conversion gain of 6.4 V/V rms at 900 MHz and assuming a maximum output of 2.9 V with a 3 V supply, has a maximum input of 2.9 V rms/6.4 or 450 mV rms. FILTERING An important aspect of rms-dc conversion is the need for averaging (the function is root-mean-square). The on-chip averaging in the square domain has a corner frequency of approximately 150 kHz and is sufficient for common modulation signals, such as CDMA, WCDMA, and QPSK/QAM-based OFDM (for example, WLAN and WiMAX). It ensures the accuracy of rms measurement for these signals; however, it leaves significant ripple on the output. To reduce this ripple, an external shunt capacitor can be used at the output to form a low-pass filter with the on-chip 1 k resistance (see the Selecting the Output Low-Pass Filter Network section). Rev. A | Page 14 of 24 ADL5500 APPLICATIONS BASIC CONNECTIONS Figure 33 shows the basic connections for the ADL5500. The device is powered by a single supply of between 2.7 V and 5.5 V with a quiescent current of 1.0 mA. The VPOS pin is decoupled using 100 pF and 0.1 F capacitors. The ADL5500 RF input does not require external termination components because it is internally matched for an overall broadband input impedance of 50 . +VS 2.7V TO 5.5V 100pF 0.1F LINEARITY Because the ADL5500 is a linear-responding device, plots of output voltage vs. input voltage result in a straight line. It is more useful to plot the error on a logarithmic scale, as shown in Figure 35. The deviation of the plot for the ideal straight-line characteristic is caused by output clipping at the high end and by signal offsets at the low end. However, it should be noted that offsets at the low end can be either positive or negative; therefore, this plot could also trend upwards at the low end. Figure 10 through Figure 15 show error distributions for a large population of devices. 3 4 ADL5500 VRMS CFLT 05546-033 1 VRMS VPOS 2 2 COMM RFIN 3 RFIN 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 3900MHz 1 Figure 33. Basic Connections for ADL5500 ERROR (dB) OUTPUT SWING At 900 MHz, the output voltage is nominally 6.4 times the input rms voltage (a conversion gain of 6.4 V/V rms). The output voltage swings from near ground to 4.9 V on a 5.0 V supply. Figure 34 shows the output swing of the ADL5500 to a CW input for various supply voltages. It is clear from Figure 34 that operating the device at lower supply voltages reduces dynamic range as the output headroom decreases. 10 5.5V 5.0V 2.7V 3.0V 0 -1 -2 05546-007 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 35. Representative Unit, Error in dB vs. Input Level, VS = 5.0 V OUTPUT (V) 1 It is also apparent in Figure 35 that the error plot tends to shift to the right with increasing frequency. The squaring cell has an input impedance that decreases with frequency. The matching network compensates for the change and maintains the input impedance at a nominal 50 . The result is a decrease in the actual voltage across the squaring cell as the frequency increases, reducing the conversion gain. Similarly, conversion gain is less at frequencies near 100 MHz because of the small on-chip coupling capacitor. 0.1 05546-008 0.03 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 34. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V, and 5.5 V Rev. A | Page 15 of 24 ADL5500 INPUT COUPLING USING A SERIES RESISTOR Figure 36 shows a technique for coupling the input signal into the ADL5500 that can be applicable where the input signal is much larger than the input range of the ADL5500. A series resistor combines with the input impedance of the ADL5500 to attenuate the input signal. Because this series resistor forms a divider with the frequency dependent input impedance, the apparent gain changes greatly with frequency. However, this method has the advantage of very little power being tapped off in RF power transmission applications. If the resistor is large compared to the transmission line's impedance, the VSWR of the system is relatively unaffected. The output of the ADL5500 can be filtered by placing a capacitor between VRMS (Pin 1) and ground. The combination of the on-chip 1 k output series resistance and the external shunt capacitor forms a low-pass filter to reduce the residual ac. Table 4 shows the effect of several capacitor values for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. Note that large load capacitances increase the turn-on and pulse response times (see Figure 29 and Figure 30). Table 4. Waveform and Output Filter Effects on Residual AC Waveform 64QAM (7.4 dB CF) CFILT 0.01 F Output V dc 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 Residual AC mV p-p mV rms 7.0 1.4 7.4 1.5 7.6 1.6 6.7 1.4 7.2 1.5 7.4 1.5 10 1.7 16 2.4 45 5.6 7 1.5 9 1.6 14 2.3 46 6 85 13 191 27 17 3 31 5 68 9 RFIN RSERIES RFIN 05546-036 0.1 F ADL5500 Figure 36. Attenuating the Input Signal MULTIPLE RF INPUTS Figure 37 shows a technique for combining multiple RF input signals to the ADL5500. Some applications can share a single detector for multiple bands. Three 16.5 resistors in a T-network combine the three 50 terminations (including the ADL5500). The broadband resistive combiner ensures each port of the T-network sees a 50 termination. Because there is only 6 dB of isolation from one port of the combiner to the other ports, only one band should be active at a time. BAND 1 DIRECTIONAL COUPLER 50 W-CDMA RL (3.4 dB CF) 0.01 F 0.1 F CDMA2000 UL (6.7 dB CF) 0.01 F 0.1 F POWER CONSUMPTION AND POWER-ON/-OFF RESPONSE 16.5 16.5 RFIN BAND 2 DIRECTIONAL COUPLER 50 ADL5500 05546-051 16.5 The quiescent current consumption of the ADL5500 varies with the size of the input signal from approximately 1 mA for no signal up to 6 mA at an input level of 0.7 V rms (10 dBm, re 50 ). If the input is driven beyond this point, the supply current increases sharply (as shown in Figure 6). There is little variation in quiescent current with power supply voltage. The ADL5500 can be disabled by simply removing the power to the device. Figure 32 shows a plot of the output response to the supply being turned on (that is, VPOS is pulsed) with an output shunt capacitor of 0.01 F. Again, the turn-on time is influenced strongly by the size of the output shunt capacitor. To improve the falling edge of the supply gating response and the pulse response, a resistor can be placed in parallel with the output shunt capacitor. The added resistance helps discharge the capacitor. Although this method reduces the power-off time, the added load resistor also attenuates the output (see the Output Drive Capability and Buffering section). Figure 37. Combining Multiple RF Input Signals SELECTING THE OUTPUT LOW-PASS FILTER NETWORK The ADL5500's internal filter capacitor provides averaging in the square domain but leaves some residual ac on the output. Signals with high peak-to-average ratios, such as W-CDMA or CDMA2000, can produce ac-residual levels on the ADL5500 dc output. To reduce the effects of these low frequency components in the waveforms, some additional filtering is required. Rev. A | Page 16 of 24 ADL5500 OUTPUT DRIVE CAPABILITY AND BUFFERING The ADL5500 is capable of sourcing an output current of approximately 3 mA. The output current is sourced through the on-chip 1 k series resistor; therefore, any load resistor forms a voltage divider with this on-chip resistance. It is recommended that the ADL5500 drive high resistive loads to preserve output swing (preferably >100 k). If an application requires driving a low resistance load, a simple buffering circuit can be used, as shown in Figure 40. Similar circuits can be used to increase or decrease the nominal conversion gain (see Figure 38 and Figure 39). In Figure 39, the AD8031 buffers a resistive divider to give half of the slope. In Figure 38, the op amp's gain of two doubles the slope. Using other resistor values, the slope can be changed to an arbitrary value. The AD8031 rail-to-rail op amp, used in these examples, can swing from 50 mV to 4.95 V on a single 5 V supply and operates at supply voltages down to 2.7 V. If high output current is required (>10 mA), the AD8051, which also has rail-to- rail capability, can be used down to a supply voltage of 3 V. It can deliver up to 45 mA of output current. 5V 0.1F 100pF VRMS OUTPUT OFFSET The ADL5500 has a 1 dB error detection range of about 30 dB, as shown in Figure 10 to Figure 15. The error is referred to the best fit line defined in the linear region of the output response. Below an input power of -20 dBm, the response is no longer linear and begins to lose accuracy. In addition, depending on the supply voltage, saturation of the output limits the detection accuracy above 10 dBm. Calibration points should be chosen in the linear region, avoiding the nonlinear ranges at the high and low extremes. 10 1 OUTPUT (V) 0.1 0.01F VPOS VRMS ADL5500 COMM AD8031 12.8V/V rms 0.01 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 INPUT (dBm) Figure 41. Output vs. Input Level Distribution of 55 Devices, Frequency 900 MHz, Supply 3.0 V 5k 05546-037 5k Figure 38. Output Buffering Options, Slope of 12.8 V/V rms at 900 MHz 5V 0.1F 100pF VPOS VRMS 0.01F 4k 5k COMM ADL5500 AD8031 3.2V/V rms 05546-038 Figure 41 shows the distribution of the output response vs. the input power for multiple devices. The ADL5500 loses accuracy at low input powers as the output response begins to fan out. As the input power is reduced, the spread of the output response increases along with the error. Although some devices follow the ideal linear response at very low input powers, not all devices continue the ideal linear regression to a near 0 V y-intercept. Some devices exhibit output responses that rapidly decrease and some flatten out. With no RF signal applied, the ADL5500 has a typical output offset of 40 mV (with a maximum of 150 mV). Figure 39. Output Buffering Options, Slope of 3.2 V/V rms at 900 MHz 5V 0.1F 100pF VPOS VRMS 0.01F ADL5500 COMM AD8031 6.4V/V rms Figure 40. Output Buffering Options, Slope of 6.4 V/V rms at 900 MHz 05546-039 Rev. A | Page 17 of 24 05546-040 ADL5500 DEVICE CALIBRATION AND ERROR CALCULATION Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. In general, calibration is performed by applying two input power levels to the ADL5500 and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear operating range of the device. The best fit line is characterized by calculating the slope and intercept using the following equations: Slope = (VRMS2 - VRMS1)/(VIN2 - VIN1) Intercept = VRMS1 - (Slope x VIN1) where: VIN is the rms input voltage to RFIN. VRMS is the voltage output at VRMS. Once slope and intercept have been calculated, an equation can be written that allows calculation of an (unknown) input power based on the measured output voltage. VIN = (VRMS - Intercept)/Slope (3) (1) (2) Figure 42 also includes error plots for the output voltage at -40C and +85C. These error plots are calculated using the slope and intercept at +25C. This is consistent with calibration in a mass-production environment where calibration at temperature is not practical. CALIBRATION FOR IMPROVED ACCURACY Another way of presenting the error function of the ADL5500 is shown in Figure 43. In this case, the dB error at hot and cold temperatures is calculated with respect to the transfer function at ambient. This is a key difference in comparison to the previous plots. Up to now, the errors have been calculated with respect to the ideal linear transfer function at ambient. When this alternative technique is used, the error at ambient becomes equal to 0 by definition (see Figure 43). This plot is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) response at ambient. The linearity and dynamic range tend to be improved artificially with this type of plot because the ADL5500 does not perfectly follow the ideal linear equation (especially outside of its linear operating range). Achieving this level of accuracy in an end application requires calibration at multiple points in the device's operating range. In some applications, very high accuracy is required at just one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. The ADL5500 offers a tight error distribution in the high input power range, as shown in Figure 43. The high accuracy range, centered around +3 dBm at 900 MHz, offers 8.5 dB of 0.1 dB detection error over temperature. Multiple point calibration at ambient temperature in the reduced range offers precise power measurement with near 0 dB error from -40C to +85C. 3 For an ideal (known) input power, the law conformance error of the measured data can be calculated as ERROR (dB) = 20 x log [(VRMS, MEASURED - Intercept)/(Slope x VIN, IDEAL)] (4) Figure 42 includes a plot of the error at 25C, the temperature at which the ADL5500 is calibrated. Note that the error is not zero. This is because the ADL5500 does not perfectly follow the ideal linear equation, even within its operating region. The error at the calibration points is, however, equal to zero by definition. 3 2 2 1 ERROR (dB) +85C +25C 1 0 -40C ERROR (dB) +85C 0 -40C +25C -1 -1 -2 05546-052 -2 05546-053 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 42. Error from Linear Reference vs. Input at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 900 MHz, Supply 5.0 V -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 43. Error from +25C Output Voltage at -40C, +25C, and +85C After Ambient Normalization, Frequency 900 MHz, Supply 5.0 V Rev. A | Page 18 of 24 ADL5500 The high accuracy range center varies over frequency. At 900 MHz, the region is centered at approximately 3 dBm. At higher frequencies, the high accuracy range is centered at higher input powers (see Figure 16 to Figure 21). ERROR (dB) 3 2 DRIFT OVER A REDUCED TEMPERATURE RANGE Figure 44 shows the error over temperature for a 1.9 GHz input signal. Error due to drift over temperature consistently remains within 0.25 dB and only begins to exceed this limit when the ambient temperature goes above +50C and below -10C. For all frequencies using a reduced temperature range, higher measurement accuracy is achievable. 1.00 0.75 0.50 0.25 0 +85C +70C +50C +30C +25C +15C 0C -10C -25C -40C 1 0 -1 -2 05546-042 -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 45. Temperature Drift Distributions for Six Devices at -40C, +25C, and +85C After Ambient Normalization, Frequency 5.0 GHz, Supply 5.0 V 3 ERROR (dB) 2 -0.25 -0.50 05546-041 1 -0.75 -1.00 -20 ERROR (dB) 0 -15 -10 -5 0 5 10 15 INPUT (dBm) -1 Figure 44. Typical Drift at 1.9 GHz for Various Temperatures -2 OPERATION ABOVE 4.0 GHz The ADL5500 works at frequencies above 4.0 GHz, but exhibits slightly higher output voltage temperature drift. Figure 45 and Figure 46 show the error distributions of six devices at 5.0 GHz and 6.0 GHz over temperature. Although the temperature drift is larger than at lower frequencies, the error distributions at each temperature remain tight throughout the central linear region. Due to the repeatability of the drift from part-to-part, compensation can be applied to reduce the effects of temperature drift. -3 -25 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 46. Temperature Drift Distributions for Six Devices at -40C, +25C, and +85C After Ambient Normalization, Frequency 6.0 GHz, Supply 5.0 V DEVICE HANDLING The wafer-level chip scale package consists of solder bumps connected to the active side of the die. The part is lead-free with 95.5% tin, 4.0% silver, and 0.5% copper solder bump composition. The WLCSP can be mounted on printed circuit boards using standard surface-mount assembly techniques; however, caution should be taken to avoid damaging the die. See the AN-617 Application Note for additional information. WLCSP devices are bumped die; therefore, the exposed die can be sensitive to light, which can influence specified limits. Lighting in excess of 600 LUX can degrade performance. Rev. A | Page 19 of 24 05546-043 ADL5500 EVALUATION BOARD Figure 48 shows the schematic of the ADL5500 evaluation board. The layout and silkscreen of the evaluation board layers are shown in Figure 49 to Figure 52. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.01 F capacitors. Table 5 details the various configuration options of the evaluation board. Problems caused by impedance mismatch can arise using the evaluation board to examine the ADL5500 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board, can cause these problems. A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original signal incident at the board. The resultant voltage varies with both cable length and frequency dependence on the relative phase of the initial and reflected signals. Placing the 3 dB pad at the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable length and other fixture issues. In an actual application when the distance between ADL5500 and source is short and welldefined, this 3 dB attenuator is not needed. Land Pattern and Soldering Information Figure 47 shows the land pattern used on the ADL5500 evaluation board. Pad diameters of 0.28 mm are used with a solder paste mask opening of 0.38 mm. For the RF input trace, a trace width of 0.30 mm is used, which corresponds to a 50 characteristic impedance for the dielectric material being used (FR4). All traces going to the pads are tapered down to 0.15 mm. For the RFIN line, the length of the tapered section is 0.20 mm. 0.30 mm (50 ) 0.20 mm 0.28 mm 0.15 mm VPOS RFIN 0.50 mm 0.50 mm 0.38 mm (PASTE MASK OPENING) VRMS COMM 0.15 mm GROUND PLANE Figure 47. Land Pattern Used on the ADL5500 Evaluation Board TO EDGE CONNECTOR R6 (OPEN) R3 0 VRMS C4 10nF R8 (OPEN) 1 ADL5500 VRMS VPOS 4 C1 100pF C2 0.1F VPOS Figure 48. Evaluation Board Schematic Table 5. Evaluation Board Configuration Options Component VPOS, GND C1, C2 R3, R8, C4 Description Ground and Supply Vector Pins. Power Supply Decoupling. The nominal supply decoupling of 0.01 F and 100 pF. Output Filtering. The combination of the internal 1 k output resistance and C4 produce a low-pass filter to reduce output ripple. The output can also be scaled down using the resistor divider pads, R3 and R8. In addition, resistors and capacitors can be placed in C4 and R8 to load test VRMS. Alternate Interface. R6 allows VOUT to be accessible from the edge connector, which is only used for characterization. Default Condition Not Applicable C1 = 0.01 F (Size 0402) C2 = 100 pF (Size 0402) R3 = 0 (Size 0402) R8 = Open (Size 0402) C4 = 10 nF (Size 0402) R6 = Open (Size 0402) R6 Rev. A | Page 20 of 24 05546-044 2 COMM RFIN 3 RFIN 05546-054 ADL5500 05546-045 Figure 49. Layout of Component Side (WLCSP) Figure 51. Silkscreen of Component Side (WLCSP) Figure 50. Layout of Circuit Side (WLCSP) 05546-046 Figure 52. Silkscreen of Circuit Side (WLCSP) Rev. A | Page 21 of 24 05546-048 05546-047 ADL5500 OUTLINE DIMENSIONS 1.010 0.960 SQ 0.910 0.381 0.356 0.331 0.675 0.596 0.516 SEATING PLANE 0.345 0.295 0.245 0.50 BSC BALL PITCH TOP VIEW (BALL SIDE DOWN) A1 BALL CORNER 2 1 A B Figure 53. 4-Ball Wafer-Level Chip Scale Package [WLCSP] (CB-4) Dimensions shown in millimeters ORDERING GUIDE Model ADL5500ACBZ-P7 1 ADL5500ACBZ-P21 ADL5500-EVALZ1 1 111105-0 0.270 0.240 0.210 BOTTOM VIEW (BALL SIDE UP) 0.030 NOM COPLANARITY Temperature Range -40C to +85C -40C to +85C Package Description 4-Ball WLCSP, 7" Pocket Tape and Reel 4-Ball WLCSP, 7" Pocket Tape and Reel Evaluation Board Package Option CB-4 CB-4 Branding Q06 Q06 Ordering Quantity 3,000 250 Z = Pb-free part. Rev. A | Page 22 of 24 ADL5500 NOTES Rev. A | Page 23 of 24 ADL5500 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05546-0-2/06(A) Rev. A | Page 24 of 24 |
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